1. Field of the Invention
The present invention relates to a method of fabricating salicide and self-aligned barrier simultaneously. The fabricating of thin film Ti silicide is difficult and the surface is rough in the prior art whereas the present invention provides a method to overcome these problems. Because Si and Al intermix with each other, `spike` is thus formed penetrating source/drain region. In order to form the barrier layer to prevent the mixture, the prior art ether deposits TiN or utilize Ti nitridation. The former can hardly control the thickness of TiN in contact hole while the later must utilize another RTP to generate TiN, both may decrease the yield. The present invention utilize RTP only once and TiN is deposited all over Ti film so the thickness of TiN is easily controlled and the yield would not be decreased.
2. Description of the Prior Art
The conventional contact structure using a self-aligned silicide is described as following sequences of processes:
1. After the source and drain regions have been implanted to form the source/drain junctions, the poly-Si sidewall spacers 110 are formed (FIG. 1a).The spacer is made of SiO.sub.2. Note that side wall oxidation structures along the gate (known as oxide spacers 110) are used to prevent the gate and source/drain areas from being electrically connected. Following the silicide formation, a selective etch removes the unreacted metal without attacking the silicide.
2. The metal used to form the silicide is deposited all over the topography to form a film 120 of metal which can be Ti, Co or Ni . . . etc. (FIG. 1b)
3. The wafer 125 is heated by rapid thermal process (RTP), which causes the silicide reaction to occur wherever the metal film is in contact with the silicon. The configuration mentioned above is shown as 130a in FIG. 1c. The metal remains unreacted everywhere else and is shown as 130b in FIG. 1c.
4. The unreacted metal is selectly removed through the use of an etchant that dose not attack the silicide, the silicon substrate, or the SiO.sub.2. As a result, each exposed source and drain region is now completely covered by silicide, but there is no film elsewhere (FIG. 1d).
5. A dielectric layer is deposited onto the silicide, and contact holes are opened in it down to the silicide layer.
6. Deposit a layer of titanium all over the topography by DC magnetron sputtering followed by a process of RTP in the chamber that containing N.sub.2 or NH.sub.3. A diffusion barrier layer--TiN is thus formed over the silicide and is shown as TiN layer 160 in FIG. 1e and dielectric layer mentioned in the previous step is shown as dielectric layer 150 in FIG. 1e.
The implement of TiN layer can utilize the other method: Sputtering deposit TiN into contact hole 155 shown in FIG. 1g to form the TiN layer 165. The advantage is the spare of RTP, whereas, especially when the contact size is small, it is hard to control the thickness of TiN layer 165 in the contact hole by sputtering deposition.
7. Having deposited W-plug into the contact holes over the TiN layer, metal-Al is deposited over W-plug and the TiN layer. By etching the unwanted part of aluminum, the unwanted TiN layer is removed too. Thus the Al layer is made in contact with the suicide through W-plug and the Al conducting line is shown as 170 in FIG. 1f.
The configuration mentioned above is called salicide, wherever TiSi.sub.2 and CoSi.sub.2 are attractive for the salicide application because it exhibits low resistivity, and because it can reduce native-oxide layers (making it the only known refractory metal that can reliably form a silicide on both polycrystalline and single-crystal silicon through a thermal reaction). Therefore TiSi.sub.2 and COSi.sub.2 are widely used in the salicide application nowadays. Furthermore, devices fabricated with titanium silicide on the gate electrode are more resistant to high-field-induced hot-electron degradation than are conventional poly-Si gate devices. It is conjectured that the TiSi.sub.2 and COSi.sub.2 are effective getteres for the hydrogen atoms introduced during the hydrogen annealing. Less hydrogen is thus incorporated into the gate oxide, and this improves the hot-electron reliability.
On the other hand, to prevent the widely used silicide material-Ti from intermixing with interconnect metal-Al, diffusion barrier layer-TiN is deposited between these two kinds of metal. The TiN layer can be formed by sputtering from a TiN target in an inert or by the procedure of rapid thermal process (RTP) of Ti in an nitrogen ambient. The procedure is sophisticated, especially, and it is hard to control the thickness of the diffusion barrier layer owing to the contact size. Besides, in some application utilizing high aspect ratio contact process (e.g. the process of DRAM . . . etc.), it is hard to form enough thickness of diffusion barrier layer-TiN, so that the difficulty of the successive processes is raised. Furthermore, in the conventional process forming thinner Ti film and narrower gate-source/drain region, it is difficult to form Ti silicide and the resistivity of the Ti silicide is hard to reduce. In addition, the surface of silicide is rough and the dielectric layer over silicide is thus rough too. In wiring processes, it is desirable that the dielectric layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surface. Also, rough surface topography results in poor step coverage by subsequently deposited layers, discontinuity of layers across steps, and void formation between topographic features. Poor step coverage by deposited layers and void formation between topographic features result in degraded process yield and poorer reliability of integrated circuits. In addition, RTP is used twice in the prior art, because the thermal control is still not perfect, the yield maybe decreases.